Phase regulating circuit with a time-delay element

ABSTRACT

A phase-locked loop with a delay element (DLL) is described which is essentially characterized in that the delay element ( 3 ) has a chain of a number n delay units ( 33   n ), the outputs ( 34   n ) of which are fed to a locking monitoring circuit ( 4 ) which determines whether the delay time T delay  of the delay element ( 3 ) lies within a range a*T period &lt;T delay &lt;b*T period , where 0.5&lt;a&lt;1 and 1&lt;b&lt;2, and wherein the locking monitoring circuit ( 4 ) performs a correction of this delay time when this condition is not met.

BACKGROUND OF THE INVENTION

The present invention relates to the field of phase-locked loops.

Unlike a phase-locked loop (PLL) with a self-oscillating oscillator, aphase-locked loop with a delay element (i.e., a delay locked loop—DLL)has the problem that the delayed output signals of the delay element areindistinguishable for all delays that correspond to an integer multipleof the clock pulse of the input signal. Therefore, the danger existsthat the delay time will be set as an indeterminate integer multiple ofthe period of the input signal.

To prevent this from occurring, one known method is to limit thepossible delay time of the delay element. However, this measure has thedisadvantage that the frequency range is significantly limited.Especially in the case of integrated circuits, there is the additionalproblem that absolute precision is required for the limiter. If theratio of the signal to the clock pulse space of the input signaldeviates from 50%, an additional downward limitation of the delay timeis required, with the result that the frequency range is limited stillfurther.

Another known approach avoids the setting of the delay time as anindeterminate integer multiple of the period of the input signal bygenerating an allocation or detection of the association of the edges ofthe output signal with the edges of the input signal. However, thisapproach is quite complex and expensive, and almost impossible toimplement, especially at high frequencies.

Therefore, there is a need for a phase-locked loop in whichnonpermissible delay times are detected and eliminated by appropriatecorrections.

SUMMARY OF THE INVENTION

This purpose is achieved with a phase-locked loop of the type referredto in the preamble according to claim 1 wherein the delay element has achain of a number n delay units, the outputs of which are fed to alocking monitoring circuit which determines whether the delay timeT_(delay) of the delay element relative to the period T_(period) of aninput signal lies within a range(a*T_(period))<T_(delay)<(b*T_(period)), where 0.5<a<1 and 1<b<2, andwhere the locking monitoring circuit performs a correction of the delaytime when this condition is not met.

These and other objects, features and advantages of the presentinvention will become more apparent in light of the following detaileddescription of preferred embodiments thereof, as illustrated in theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a schematic circuit diagram of such an embodiment;

FIG. 2 is a schematic circuit diagram of a delay element; and

FIG. 3 is a schematic circuit diagram of a locking monitor circuit.

DETAILED DESCRIPTION OF THE INVENTION

The circuit shown in FIG. 1 includes a phase detector 1, a loop filter2, a delay element 3 with a chain of delay units, and a locking monitorcircuit 4.

An input signal with a reference frequency f_(ref) is applied to a firstinput 11 of the phase detector 1, and to a first input 31 of the delayelement 3. The phase detector has a second input 12 for a feedbacksignal from the delay element 3 with a frequency f_(delay) which is fedthrough an output 33 of the delay element 3. The delay units containedin the delay element are each connected through one of connecting lines34 n(n=1, 2, 3, . . . ) to the locking monitoring circuit 4 and acircuit output 35.

The loop filter 2 has a first positive input 21 and a second negativeinput 22. A first output 13 of the phase detector 21 is applied to thefirst input 21, while the second input 22 of the loop filter 2 isconnected to a second output 14 of the phase detector 1. The output 23of the loop filter 2 is connected to a second input 32 of the delayelement 3 for a control voltage.

Finally, a first output 41 of the locking monitor circuit 4 is connectedto a positive (V+) input 15, while a second output 42 of the lockingmonitor circuit 4 is connected to a negative (V−) input 16 of the phasedetector 1.

FIG. 2 is a schematic circuit diagram of one example of the delayelement 3. It is composed of a series circuit with n delay units 33n(n=1, 2, . . . ) which are each formed by two series-connectedinverters J1, J2. The input of the first delay unit 331 is connected tothe first input 31 of the delay element 3, while the output of the lastdelay unit 33 n is applied to the output 33 of the delay element 3. Theoutput of each delay unit 33 n is connected to one of connecting lines34 n leading to the locking monitor circuit 4. Finally, the invertersJ1,J2 of the delay units 33 n are controlled through a common controlline connected to the second input 32 of the delay element 3.

FIG. 3 is an example of a schematic circuit diagram of the lockingmonitor circuit 4. The circuit includes four stages S1 through S4. Firststage S1, which serves to evaluate “high” states of delay units 33 n,creates an AND relation of the signals fed through connecting lines 34n(n=1, 2, 3, . . . ) with a first AND element 43, where a factor of, forexample, (0.8*n) signals is employed. Second stage S2, which serves toevaluate the “low” states of delay units 33 n, inverts these suppliedsignals (factor multiplied by n) and then creates a second AND relationto a second AND element 44. The outputs of the two AND elements 43, 44are gated to an OR element 45, the output of which is connected to thesecond output 42 of the locking monitor circuit 4.

The third stage S3 evaluates the falling edges of the outputs of thedelay units 33 n and includes n first AND elements 46 n, the outputs ofwhich are each fed to a second OR element 47. Third stage S3 alsoincludes n third AND elements 48 n(n=1, 2, 3, . . . ), the outputs ofwhich are each fed to a fourth OR element 49. Finally, the outputs ofthe second and fourth OR elements 47 and 49 are input to an AND element50. Two successive outputs e, e+1, . . . ; g, g+1, . . . of certaindelay units 33 n of delay element 3 are applied to the two inputs of thefirst and third AND elements 46 n, 48 n, where in each case a firstinput is inverted and a second input is noninverted. Selection of theoutputs is described in more detail below.

Fourth stage S4 evaluates the rising edges of the outputs of delay units33 n and is designed analogously to third stage S3 with analogouselements 51 n, 52, 53 n, 54,55(n=1, 2, 3, . . . ). The same is true ofthe signals applied to the inputs of the first and third AND elements 51n, 53 n. The only difference is that the first inputs of the first andthird AND elements 51 n, 53 n are noninverting, while the second inputsof these elements are inverting. The outputs of the AND elements 50 and55 of the third or fourth stage are fed to a fifth OR element 56, theoutput of which is connected to the positive first output 41 of thelocking monitor circuit 4.

The following discussion presents the functions and operation (inprinciple) of the phase-locked loop.

Based on the fact that the delay element 3 is formed by a chain of ndelay units 33 n (FIG. 2), the state of the outputs of these delay unitsat the connecting lines 34 n may be employed to detect impermissibledelay times, and to cause the locking monitor circuit 4 to performcorresponding corrections.

To accomplish this, the locking monitor circuit 4 determines whether thedelay time T_(delay) of the delay element 3 lies in a range(a*T_(period))<T_(delay)<(b*T_(period)) relative to the periodT_(period) of the input signal, where 0.5<a<1 and 1<b<2. The precisevalues of a and b depend on the implementation of the locking monitorcircuit 4, which in turn is essentially determined by thecharacteristics of the phase detector 1.

If the delay element 3 includes n delay units 33 n, then a maximum delaytime of (n*T_(period)) may be detected by the locking monitor circuit 4.In practice, this is not a limitation since (T_(delay unit)<T_(period))applies for almost all types of delay units.

The determination as to whether T_(delay)<(a*T_(period)) may be madebased on the number of like successive states in the chain of n delayunits 33 n.

Given a clock pulse/space ratio of 50% of the input signal, this is(0.5*n) delay units for a =1, and (1*n) delay units for a =0.5. Thismeans that, given a number m of successive delay units of the samestate, where (0.5*n)<m<n, the locking monitor circuit 4 must give thephase detector 1 the priority signal “−”. This means that the signal ofthe locking monitor circuit 4 has priority over the signal of the phasedetector 1. As a result, the delay time is increased until theabove-mentioned condition is no longer met and the phase detector 1itself takes over the fine adjustment of the delay time.

When a clock pulse/space ratio is not equal to 50%, both states (low andhigh) of the input signal must be monitored, and the results OR-gated.This means that each of the two results for low or high states mayproduce a signal at the first output 41 of the locking monitor circuit4. Given a clock pulse/space ratio not equal to 50%, the adjustmentrange of the phase detector 1 is limited. This limitation is due to thefact that the phase detector 1 makes its decision not solely based on,for example, a rising signal edge, as is generally the case with PLLcircuits. Instead, additional time information between two homogeneousedges is required, which indicates the end of the time range valid forevaluation. Ideally, this time information is situated precisely in themiddle between two homogeneous edges. However, time information of thissort may be obtained only with considerable complexity and cost. Forthis reason, another edge type, such as a falling edge, is preferablyused instead. When in this case the clock pulse/space ratio is not equalto 50 percent, the time range valid for edge evaluation is limited. Thisis based on the fact that the edge of the other type does not lieprecisely in the middle of the period.

In addition, the value of a must be chosen, such thata>(T_(high)/T_(period)) AND a>(T_(low)/T_(period)) is true.

In principle, the values a and b are variable and are determined by theimplementation of the circuit, that is, the number n delay units 33 n,the number of successively monitored units, and the capture range of thephase detector 1. To the extent the capture range of the phase detector1 is also a function of the clock pulse/space ratio, as is true in thecase described above, the values of a and/or b are also determined bythis ratio.

The determination as to whether (T_(delay)>b*T_(period)) may also bemade based on the number of like successive states in the chain of ndelay units 33 n. For the limit b=2, n/4 successive delay units musthave the same state, while for b=1 this number must be n/2. In otherwords, if p successive delay units never have the same statesimultaneously, where (n/4)<p<(n/2), then the locking monitor circuit 4sends a priority “+” signal through the output 41 to the phase detector1 (that is, the signal of the locking monitor circuit 4 has priorityover the signal of the phase detector 1) in order to shorten the delaytime.

Given a clock pulse/space ratio not equal to 50%, both states, namelylow and high, must be monitored, as was true when monitoringT_(delay)<(a*T_(period)), where again the results of both tests must beOR-gated.

In one embodiment, this decision process proceeds in four stages. Thefirst and second stages S1 and S2 test for the presence of the conditionT_(delay)<(a*T_(period)). When this condition is detected in at leastone of these two stages, the priority signal “−” having priority overthe signal of the phase detector 1 is set at the second output 42 of thelocking monitor circuit 4. The stages S3 and S4 of the decision processtest for the presence of the condition T_(delay)>(b*T_(period)). If thiscondition is detected in at least one of the stages S3 and S4, thepriority signal “+” relative to the signal of the phase detector 1 isset at the first output 41 of the locking monitor circuit 4. Thisfour-stage test is required only when the clock pulse/space ratio is notequal to 50 percent. When, however, this ratio does equal 50 percent, atwo-stage decision process is sufficient since the results of the firstand second stages S1, S2 are identical with the results of the third andfourth stages S3, S4.

One disadvantage of this method is that, as the clock pulse asymmetry ofthe input signal increases, the value selected for b must become largerand larger. At the limit of 25% or 75% for the clock pulse/space ratio,b=2 applies; given an even greater asymmetry, this method is no longerpossible.

It is therefore preferable to determine whether T_(delay)>(b*T_(period))by a different method. Instead of evaluating successive states, thesignal transitions (edges) are detected in the chain of n delay units 33n. The evaluation may be limited to one type of edges, that is, risingor falling. It is expedient to take the type of edges which are alsoutilized by the phase detector 1 as the time-critical edges. What isdetected is whether the same type of edges appear in two differentregions in the chain of n delay units 33 n. For b=1, the beginning ofregion 1(e) extends to the end of region 2(h) over all n delay units.For b=2, the beginning of region 1(e) extends to the end of region 2(h)over n/2 delay units. What must be true for the length of the tworegions is that it must be more than one quarter the distance from thebeginning of region 1(e) to the end of region 2(h): (f−e)>(h−e)/4 AND(h−g)>(h−e)/4.

Here (e) is the number of the delay unit at the beginning of region 1,(f) is the number of the delay unit at the end of region 1, (g) is thenumber of the delay unit at the beginning of region 2, and (h) is thenumber of the delay unit at the end of region 2.

Numbering is continuous, beginning with number 1 at the beginning of thedelay chain through number n at the end of the chain.

In the event one type of edge appears simultaneously in both the regionsof the delay element 3 so defined, the locking monitor circuit 4 sends apriority “+” signal to phase detector 1 through the first output 41(that is, the signal of the locking monitor circuit 4 has priority overthe signal of phase detector 1) so as to reduce the delay timeT_(delay).

Essentially, only one type of the phase detector 1 may be employed whichcovers a maximum range of less than 360 degrees. Sequential phasedetectors with a coverage of 720 degrees or more, often used in PLLs,are less suited for this purpose.

An ideal phase detector 1 would have a coverage range of −180+e degreesto +180−e degrees, where e>0 and e−>0. For the principle presentedaccording to the invention, a phase detector of this type is especiallywell suited for every clock pulse/space ratio. There is some technicaldifficulty, however, in obtaining information on one half the clockperiod T_(period)/2 since, as the above explanation indicates,additional time information is required.

A preferred approach is therefore to employ a phase detector for whichthe coverage region is controlled by both edge types. Given anasymmetrical clock pulse/space ratio, the coverage region of such aphase detector is also asymmetrical; it is then

−360°*(1−[T_(high)/T_(period)])<coverageregion<360°*[T_(high)/T_(period)] or

−360°*(1−[T_(low)/T_(period)])<coverageregion<360°*[T_(low)/T_(period)], depending on which edge type is usedto set or reset the “+”/“−” signals.

Care must be taken that the value of b, and thus the size of thedetection regions (f−e) and (h−g) are chosen such that the lockingmonitor circuit 4 releases control of the phase detector 1 only when thephase position of the input signals of the phase detector 1 lies withinthe coverage range of the detector. If this rule is ignored, control ofthe locked state may not be achieved cleanly and may oscillate. Althoughthe locking monitor circuit 4 then brings T_(delay) closer toT_(period), this is not close enough for the phase detector 1. It maystill be possible for T_(delay) to enter the capture range of the phasedetector and allow the control to lock in. However, it is also possiblefor T_(delay) to drift again from the capture range. In this case, thecontrol oscillates and is not able to lock in.

If, for example (h−e)=(0.8*n) is chosen, the result is a maximum phaseposition of 90° at the phase detector 1. In this case, the minimum ormaximum allowed clock pulse l space ratio is 25% or 75%, respectively,depending on the type of edges which are evaluated in phase detector 1.

The phase-locked loop according to the invention is preferably suitedfor generating shifted clock pulses in multiclock systems, orclockjitterers, and clock multipliers, clock balancers to obtain 50%clock pulse/space ratios from any asymmetrical clock pulses.

Although the present invention has been shown and described with respectto several preferred embodiments thereof, various changes, omissions andadditions to the form and detail thereof, may be made therein, withoutdeparting from the spirit and scope of the invention.

1. A phase-locked loop, comprising: a phase detector, loop filter, anddelay element, wherein the delay element has a chain of n delay units,the outputs of which are fed to a locking monitoring circuit whichdetermines whether the delay time T_(delay) of the delay element lieswithin a range a*T_(period)<T_(delay)<b*T_(period) relative to a periodT_(period) of an input signal at the phase detector, where 0.5<a<1 and1<b<2, and where the locking monitoring circuit performs a correction ofthe delay time when this condition is not met.
 2. The phase-locked loopof claim 1, wherein the condition that T_(delay)<a*T_(period) is testedby a number m of successive delay units with the same state.
 3. Thephase-locked loop of claim 2, wherein given a clock pulse-/-space ratiofor the input signal of approximately 50 percent, the locking monitorcircuit 4 performs a correction by signaling the phase detector toincrease the delay time when the condition 0.5*n<m<n is true.
 4. Thephase-locked loop of claim 2, wherein given a clock pulse-/-space ratiofor the input signal not equal to 50 percent, the low and high states ofthe delay units are monitored, and the results are OR-gated, with thevalue of a being selected such that the condition a>T_(high)/T_(period)AND a>T_(low)/T_(period) is true.
 5. The phase-locked loop of claim 1,wherein the condition T_(delay)>b*T_(period) is tested by a number p ofsuccessive delay units which at no time have the same state.
 6. Thephase-locked loop of claim 5, wherein given a clock pulse-/-space ratiofor the input signal of approximately 50 percent, the locking monitorcircuit performs a correction by signaling the phase detector (1) toreduce the delay time when the condition n/4<p<n/2 is true.
 7. Thephase-locked loop of claim 5, wherein given a clock pulse-/-space ratiofor the input signal that is not equal to 50 percent, the low and highstates of the delay units are monitored, and the results OR-gated. 8.The phase-locked loop of claim 1, wherein the conditionT_(delay)>b*T_(period) is determined by the same type of rising and-/orfalling signal transitions in at least two different regions of thechain of n delay units, and a correction is performed by reducing thedelay time by signaling the phase detector when one type of signaltransition occurs simultaneously in both regions of the locking monitorcircuit.
 9. The phase-locked loop of claim 8, wherein for a value b=1the beginning of a first region extends to the end of a second regionover all n delay units, while for a value b=2 the beginning of the firstregion extends to the end of the second region over n/2 delay units. 10.The phase-locked loop of claim 9, wherein the length of each of the tworegions is dimensioned such that it is more than a quarter of thedistance from the beginning of the first region to the end of the secondregion according to the following condition: (f−e)>(h−e)/4 AND(h−g)>(h−e)/4, where the values e and f indicate the number of delayunits at the beginning or end of the first region, and the values g andh indicate the number of delay units at the beginning or end of thesecond region, and the numbering of the delay units is consecutive fromnumber 1 at the beginning of the delay element (3) to number n at theend of the delay element.